Field of the Invention
The present invention relates to electronics and, more specifically but not exclusively, to electrostatic discharge (ESD) protection schemes for integrated circuits and the like.
Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Electrostatic discharge (ESD) is a transient discharge of static charge flowing through an integrated circuit (IC) that arises from either human handling or machine contact. In order to prevent damage to core circuitries, it is standard industry practice to provide ICs with built-in ESD structures designed to handle ESD events. One common technique is to employ an RC (resistance-capacitance)-triggered clamp having a shunt transistor that turns on upon the occurrence of an ESD event to provide a path that shunts the ESD voltage and current from the ESD-affected node to ground and then turns off after the ESD event is over. The shunt transistor is controlled by an RC trigger consisting of a series combination of a resistor and a capacitor that establishes an RC time constant that controls the timing of the turning on and off of the shunt transistor.
A typical IC may have a different instance of ESD circuitry for each different group of input/output (I/O) circuits in the IC, where each instance of ESD circuitry may have multiple RC-triggered clamps protecting, for example, different nodes associated with different IC power supplies. In general, it is typically desirable to minimize the amount of layout area dedicated to such ESD circuitry.